Reduced Complexity Full-Flash ADCs

• Abstract:

  This paper presents innovative schemes of “full-flash” and “subranging” A/D converter architectures. These new architectures are based on a conversion technique inferred by an electrical interpretation of the calliper rule. This kind of ADC implementation allow the dramatic reduction of the required resistors. Indeed, while a traditional full-flash or subranging ADC requires a voltage comparison scale realized by a series of 2n resistors, being n the number of bits of the resulting binary samples, the proposed architectures require only 3*2n/2 resistors. This reduction produces an obvious advantage in general case but can render possible the realization of full-flash ADC of large word lengths.
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• Download:

  IMEKO-TC4-2005-031.pdf
• DOI:

  _unreg_tc4-2005.031

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