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POWER OPTIMIZATION OF HIGH-RESOLUTION LOW-BANDWIDTH SC ΔΣ MODULATORS

Serena Porrazzo, Francesco Cannillo, Chris van Hoof
  • Abstract:
    This paper presents a procedure for the power-optimal design of high-resolution low-bandwidth switched-capacitor (SC) ΔΣ modulators (ΔΣMs). The most power efficient ΔΣ architecture is identified among single-loop switched-capacitor (SC) feedback (FB) and feed-forward (FF) topologies with different loop order N, oversampling ratio OSR, and quantizer resolution B. Based on the results obtained, an experimental prototype is implemented in a 0.18 µm CMOS process, achieving a signal-to-noise ratio (SNR) of 95 dB over a signal bandwidth fBW of 10 kHz. The prototype operates with a 1.28 MHz sampling rate and dissipates a total power of 210 µW from a 1.8V supply.
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  • DOI:
    _unreg_iwadc-2011.27

Event details:

  • IMEKO TC:
    TC4
  • Event name:
    IWADC 2011
  • Title:

    16th IMEKO International Workshop on ADC Modeling and Testing - Data Converter Design, Modeling and Testing (together with IEEE ADC Forum) (IWADC)

  • Place:
    Orvieto, ITALY
  • Time:
    30 June 2011 - 01 July 2011