COUNTER BASED FREQUENCY SYNTHESIZER

• Abstract:

  This paper describes architecture a new pure digital frequency synthesizer based on generators, counters and a register. The technique described here is much simpler then other method. Presented synthesizer is the most suitable for the design of VLSI architectures or for programmable Large Scale Integration. On the other hand, this synthesizer has a disadvantage in low output frequency, but this can be overcome by using this synthesizer together with phase locked lop.
• Keywords:

  frequency synthesizer, phase locked loop, delaylocked loop
• Download:

  PWC-2003-TC4-112.pdf
• DOI:

  _unreg_wc-2003.TC4-112

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