A 6-bit 3GS/s FLASH ADC IN BIPOLAR 0.25 µm FOR THE RADIOTELESCOPE SKA

• Abstract:

  A flash Analog to Digital Converter (ADC) at 3 Giga samples per second (GS/s) was developed using QUBIC4X which is a 0.25 µm SiGeC process from NXP Semiconductors. The ADC has a bandwidth close to 1.2 GHz with a resolution of 6-bit. The full design employs a differential structure. The ADC uses a parallel architecture consisting of the following components: track and hold, comparators, and a fat tree encoder. An embedded test system will help us to validate the data transmission, and it is made by a Linear Feedback Shift Register (LFSR). An additive scrambler block allowed us to transmit the data without an accompanying clock signal. The core of the digital circuit is in Emitter-Coupled Logic (ECL). The input is adapted to 100 Ω differential, and the outputs use standard Low Voltage Differential Signaling (LVDS). The input voltage range is about 0.5 Volts. The complete system has a power consumption of 2.6 Watts and the Effective Number of Bits (ENOB) is higher than 4.4 at 1490 MHz.
• Download:

  IMEKO-IWADC-2011-36.pdf
• DOI:

  _unreg_iwadc-2011.36

Event details:

• IMEKO TC:

  TC4
• Event name:

  IWADC 2011
• Title:

  16th IMEKO International Workshop on ADC Modeling and Testing - Data Converter Design, Modeling and Testing (together with IEEE ADC Forum) (IWADC)

• Place:

  Orvieto, ITALY
• Time:

  30 June 2011 - 1 July 2011