Skip to main content

Search Proceedings

NONIDEALITIES STUDY OF A CONTINUOUS-TIME DELTA-SIGMA MODULATOR USING VHDL-AMS MODELLING

A. Mariano, D. Dallet, Y. Deval, J-B. Bégueret
  • Abstract:
    In this paper, a complete high-speed Continuous-Time Bandpass Delta-Sigma modulator for digital receiver applications is modeled, using VHDL-AMS. The main Continuous-Time Delta-Sigma modulator’s nonidealities such as excess loop delay, clock jitter and multi-bit feedback DAC element mismatch in the modulator loop are also modeled and their effects evaluated. An accurate understanding of these non-ideal phenomena allows to estimate the limits of the modulator and hence to design more robust building-blocks.
  • Download:
  • DOI:
    _unreg_tc4-2008.038

Event details:

  • IMEKO TC:
    TC4
  • Event name:
    IWADC 2008
  • Title:

    13th IMEKO TC4 Workshop on ADC Modelling and Testing IWADC (together with XVIth IMEKO TC4 International Symposium on Electrical Measurements and Instrumentation) (IWADC)

  • Place:
    Florence, ITALY
  • Time:
    22 September 2008 - 24 September 2008