HARDWARE REDUCTION IN DELTA-SIGMA DIGITAL-TO-ANALOG CONVERTERS VIA BUS-SPLITTING

• Abstract:

  This paper discusses a bus-splitting technique for hardware reduction in error feedback digital delta-sigma modulators (DDSMs). The technique is based on error masking and is applied to DDSMs with sinusoidal inputs. We consider the components that contribute to the output signal-to-noise ratio in conventional DDSMs and review new architectures for implementing the digital algorithms without sacrificing performance.
• Download:

  IMEKO-IWADC-2011-23.pdf
• DOI:

  _unreg_iwadc-2011.23

Event details:

• IMEKO TC:

  TC4
• Event name:

  IWADC 2011
• Title:

  16th IMEKO International Workshop on ADC Modeling and Testing - Data Converter Design, Modeling and Testing (together with IEEE ADC Forum) (IWADC)

• Place:

  Orvieto, ITALY
• Time:

  30 June 2011 - 1 July 2011